1. Field of the Invention
The present invention relates to data processing systems, particularly to data processing systems provided with processors having a function of generating a start address of a program for initialization in response to a reset signal, and executing commands fetched in accordance with the start address, to set the internal state of the device proper.
2. Description of the Related Art
When a device provided with a microprocessor is powered on, the microprocessor performs a reset operation for initializing the internal state of the processor, in response to a reset signal externally given. In the reset operation, initialization in hardware is first performed in which the stored data of each memory element provided in the processor is initialized, and then initialization in software is performed in which a program for initialization is read out from an external memory, and the program is executed to set various application programs in their executable states.
The hardware initialization starts when the reset signal is asserted. When the reset signal is negated, the software initialization starts. The software initialization is performed with fetching commands of the initialization program from the address designated by a reset vector. In general, the initialization program is stored in a read-only memory (hereinafter referred to as ROM) externally connected to the processor through a bus.
In the software initialization, the processor gives the ROM a read request address via the bus. A sequence of commands of the initialization program is then read out in order and supplied to the processor via the bus. The processor having received the commands sets proper values to meet the system, in various setting registers provided in the processor, in accordance with the respective supplied commands. The processor thereby sets up an environment in which each application program is executable.
A multiprocessor system is known which includes processors connected to a common bus. The processors are made up from one master processor and the remaining slave processors, and each of the processors performs such a reset operation as described above. To reset the whole of this multiprocessor system, every processor must perform its reset operation.
For this purpose, a reset signal is asserted to all the processors, and thereby every processor performs its hardware initialization. After the reset signal is asserted for a time necessary and sufficient for initializing the stored data of the memory elements in every processor, the reset signal is negated to all the processors.
When the reset signal is negated, all the processors try to access a ROM at once, in accordance with the address designated by a reset vector, in order to perform their software initializations. The ROM connected to the common bus, however, can not simultaneously receive the accesses of the processors. Thus the processors access the ROM in order through arbitration on the common bus (bus arbitration), to read out a sequence of commands of a program necessary for software initialization.
In a system including a processor which performs such a reset operation, it is also proposed that the clock supply is stopped in the processor to reduce the power consumption of the system when the processor is out of operation even after the system is powered on. For example, in such a multiprocessor system as described above, there is the state that the master processor is in operation and the slave processors are out of operation. In this state, the clock supply in each slave processor is stopped to reduce the power consumption.
When a processor in which the clock supply is stopped is required to operate, the clock supply is restarted to start the processor. In this case, the processor being started performs its hardware initialization in response to an assertion of a reset signal, and then its software initialization in response to a negation of the reset signal. In the software initialization, the processor accesses a ROM via a bus, and reads out a sequence of commands of a necessary initialization program.
In such a conventional system as described above, however, the software initialization, which is performed subsequently to the hardware initialization, requires an access to the ROM, which is a low-speed memory device, via the bus to obtain the program necessary for the initialization. As a result, the reset operation takes a long time.
Particularly in a system in which the clock supply in a processor is temporarily stopped to reduce power consumption, if the processor is frequently stopped and started, an access to a low speed ROM must be made in every start operation. This brings about an increase in vain time for waiting for the start of the system.
Besides, in a multiprocessor system as described above wherein processors are connected to a common bus, a ROM which stores the initialization programs for the respective processors, is connected to the common bus. When accesses from the processors to the ROM concur, bus arbitration is made so that the processors may access the low speed ROM in order. Thus the time for initializing all the processors increases considerably.
Besides, in such a multiprocessor system, the respective processors are assigned different roles in general. The manners of their software initializations differ accordingly. The processors, therefore, use different programs for their software initializations. In this system, required is means for judging as to which of the different programs stored in the ROM each processor uses. As a result, the system construction becomes complicated.
It is an object of the present invention to provide data processing systems wherein the software initialization of a processor can be performed more rapidly.
It is another object of the present invention to provide data processing systems wherein the software initialization of a processor can be performed with a simpler construction.
According to an aspect of the present invention, a data processing system in which initialization in software is performed with a necessary initialization program read out from a memory after initialization in hardware has been performed in response to a reset signal, comprises an address selecting section for selecting the start address of the initialization program stored in a local memory or an external memory connected through a bus, on the basis of an address selection signal.
In this feature, when a processor in which the supply of its internal clock has been stopped after the system was powered on, is to be restarted, the processor can read out an initialization program necessary for its restarting operation, from the high-speed local memory. Thus the restarting operation can be performed rapidly. Thereby realized is a rapid restart from a state of stopping the clock for reducing the power consumption of the system.
According to another aspect of the present invention, a data processing system in which initialization in software is performed with a necessary initialization program read out from a memory after initialization in hardware has been performed in response to a reset signal, comprises an access inhibiting section for inhibiting any access request to the memory storing the initialization program, on the basis of a start inhibiting signal.
In this feature, the initialization program stored in an external memory connected through an external bus, can be transferred to a local memory while inhibiting any access request to the local memory. By this manner, in the start processing sequence when the system is powered on, the initialization program for the starting operation can be read out from the high-speed local memory, without necessity of accessing the external memory. Besides, there is no case that processors connected to the external bus start to access the external memory at once. Therefore, arbitration on the common bus becomes unnecessary, and accordingly a rapid starting operation can be performed.
Besides, in case of a multiprocessor system, means for judging as to which program each processor is to execute, becomes unnecessary. Therefore, the system construction can be simplified.